View MRF24J40-I_1023467.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MRF24J40 Data Sheet
IEEE 802.15.4TM 2.4 GHz RF Transceiver
(c) 2006 Microchip Technology Inc.
Advance Information
DS39776A
Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
*
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2006, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company's quality system processes and procedures are for its PIC(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
DS39776A-page ii
Advance Information
(c) 2006 Microchip Technology Inc.
MRF24J40
IEEE 802.15.4TM 2.4 GHz RF Transceiver
Devices Included:
* MRF24J40
RF/Analog Features:
* ISM Band 2.405-2.48 GHz Operation * -91 dBm Typical Sensitivity and +5 dBm Maximum Input Level * +0 dBm Typical Output Power and 38.75 dB TX Power Control Range * Differential RF Input/Output and Integrated TX/RX Switch * Integrated Low Phase Noise VCO, Frequency Synthesizer and PLL Loop Filter * Digital VCO and Filter Calibration * Integrated RSSI ADC and I/Q DACs * Integrated LDO * High Receiver and RSSI Dynamic Range
Features:
* Complete IEEE 802.15.4 Specification Compliant * Supports MiWiTM, ZigBeeTM and Proprietary Protocols * Simple, 4-Wire SPI Interface * Integrated 20 MHz and 32.768 kHz Oscillator Drive * 20 MHz Reference Clock Output: - Available to drive microcontroller oscillator * Supports Power-Saving mode * Low-Current Consumption, Typical 18 mA in RX mode and 22 mA in TX mode * Typical 2 A Sleep mode * Small, 40-Pin Leadless QFN 6x6 mm2 Package
MAC/Baseband Features:
* Hardware CSMA-CA Mechanism, Automatic ACK Response and FCS Check * Independent Beacon, Transmit and GTS FIFO * Hardware Security Engine (AES-128) with CTR, CCM and CBC-MAC modes * Supports all CCA modes and RSS/LQI * Automatic Packet Retransmit Capability * Supports In-Line or Stand-Alone modes for both Encryption and Decryption
Pin Diagram:
LCAP VDD NC VDD GND VDD OSC1 OSC2 VDD VDD 40 39 38 37 36 35 34 33 32 31 VDD RFP RFN VDD VDD GND GPIO0 GPIO1 GPIO5 GPIO4 1 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 RXQP RXIP LPOSC1 LPOSC2 CLKOUT GND GND NC GND VDD
40-Pin QFN
MRF24J40
11 12 13 14 15 16 17 18 19 20 GPIO2 GPIO3 RESET GND WAKE INT SDO SDI SCK CS Note: Backside center pad is GND. (c) 2006 Microchip Technology Inc.
Advance Information
DS39776A-page 1
MRF24J40
Table of Contents
1.0 Overview ...................................................................................................................................................................................... 3 2.0 External Connections ................................................................................................................................................................... 7 3.0 Memory Organization ................................................................................................................................................................... 9 4.0 Serial Peripheral Interface (SPI)................................................................................................................................................. 13 5.0 IEEE 802.15.4TM-2003 ............................................................................................................................................................... 19 6.0 Initialization................................................................................................................................................................................. 21 7.0 Transmitting and Receiving Packets .......................................................................................................................................... 29 8.0 Interrupts .................................................................................................................................................................................... 35 9.0 General Purpose I/O .................................................................................................................................................................. 39 10.0 Electrical Characteristics ............................................................................................................................................................ 41 11.0 Packaging Information................................................................................................................................................................ 45 Appendix A: Layout and Part Selection................................................................................................................................................ 47 Appendix B: MRF24J40 Schematic and Bill of Materials ..................................................................................................................... 55 Index .................................................................................................................................................................................................... 59 The Microchip Web Site ....................................................................................................................................................................... 61 Customer Change Notification Service ................................................................................................................................................ 61 Customer Support ................................................................................................................................................................................ 61 Reader Response ................................................................................................................................................................................ 62 Product Identification System............................................................................................................................................................... 63
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using.
Customer Notification System
Register on our web site at www.microchip.com to receive the most current information on all of our products.
DS39776A-page 2
Advance Information
(c) 2006 Microchip Technology Inc.
MRF24J40
1.0 OVERVIEW
Features are summarized in Table 1-1 and the pinout for this device is listed in Table 1-2. The MRF24J40 consists of four major functional blocks: 1. An SPI interface that serves as a communication channel between the host controller and the MRF24J40. Control registers which are used to control and monitor the MRF24J40. The MAC (Medium Access Control) module that implements IEEE 802.3TM compliant MAC logic. The PHY (Physical Layer) driver that encodes and decodes the analog data. The MRF24J40 is an IEEE 802.15.4-2003 compliant transceiver supporting MiWiTM, ZigBeeTM and other proprietary protocols. The MRF24J40 integrates wireless RF, PHY layer baseband and MAC layer architectures that can be combined with a simple microprocessor to apply low data rate to a multitude of applications that include home automation, consumer electronics, PC peripherals, toys, industrial automation and more. The MRF24J40 device integrates a receiver, transmitter, VCO and PLL into a single integrated circuit. It uses advanced radio architecture to minimize external part count and power consumption. The MRF24J40 MAC/baseband provides hardware architecture for both IEEE 802.15.4 MAC and PHY layers. It mainly consists of TX/RX FIFOs, a CSMA-CA controller, superframe constructor, receive frame filter, security engine and digital signal processing module. The MRF24J40 is fabricated by advanced 0.18 m CMOS process and is offered in a 40-pin QFN 6x6 mm2 package.
2. 3. 4.
The device also contains other support blocks, such as the on-chip voltage regulator, security module and system control logic.
TABLE 1-1:
DEVICE FEATURES FOR THE MRF24J40 (40-PIN DEVICE)
Features MRF24J40 Yes 20 MHz and 32.768 kHz 20 MHz Yes Typical 18 mA in RX and 22 mA in TX 2 A Typical SPI (4-wire) 40-Pin Leadless QFN 6x6 mm2
IEEE 802.15.4TM Specification Compliant Integrated Oscillator Drive Reference Clock Output Power-Saving Mode Support Current Consumption Sleep Mode Serial Communications Packages
(c) 2006 Microchip Technology Inc.
Advance Information
DS39776A-page 3
MRF24J40
FIGURE 1-1: MRF24J40 ARCHITECTURE BLOCK DIAGRAM
User Application
ZigBeeTM Protocol or MiWiTM Protocol or Proprietary Protocol
Physical Layer Driver
Interrupt
SPI Interface
Reset
TX FIFOs
Long Control Short Control Registers Registers
RX FIFO
TX MAC
Security Module
RX MAC
TX PHY
RX PHY
MRF24J40
DS39776A-page 4
Advance Information
(c) 2006 Microchip Technology Inc.
MRF24J40
1.1 Pin Descriptions
MRF24J40 PIN DESCRIPTIONS
Type Power AIO AIO Power Power Ground DIO DIO DIO DIO DIO DIO DI Ground DI DO DIO DIO DI DI Power Ground -- Ground Ground DIO AI AI AO AO Power Power AI AI Power Ground Power -- Power -- Description RF power supply. Bypass with a capacitor as close to the pin as possible. Differential RF input/output (+). Differential RF input/output (-). RF power supply. Bypass with a capacitor as close to the pin as possible. Guard ring power supply. Bypass with a capacitor as close to the pin as possible. Guard ring ground. General purpose digital I/O, also used as external PA enable. General purpose digital I/O, also used as external TX/RX switch control. General purpose digital I/O. General purpose digital I/O. General purpose digital I/O, also used as external TX/RX switch control. General purpose digital I/O. Global hardware Reset pin active-low. Ground for digital circuit. External wake-up trigger. Interrupt pin to microcontroller. Serial interface data output from MRF24J40. Serial interface data input to MRF24J40. Serial interface clock. Serial interface enable. Digital circuit power supply. Bypass with a capacitor as close to the pin as possible. Ground for digital circuit. No Connection, do not connect anything to this pin. Ground for digital circuit. Ground for digital circuit. 20/10/5/2.5 MHz clock output. 32 kHz crystal input (-). 32 kHz crystal input (+). Analog RX I channel output (+). Analog RX Q channel output (+). Power supply for band gap reference circuit. Bypass with a capacitor as close to the pin as possible. Power supply for analog circuit. Bypass with a capacitor as close to the pin as possible. 20 MHz crystal input (-). 20 MHz crystal input (+). PLL power supply. Bypass with a capacitor as close to the pin as possible. Ground for PLL. Charge pump power supply. Bypass with a capacitor as close to the pin as possible. No Connection. VCO supply. Bypass with a capacitor as close to the pin as possible. PLL loop filter external capacitor. Connected to external 180 pF capacitor.
TABLE 1-2:
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 VDD RFP RFN VDD VDD GND
Symbol
GPIO0 GPIO1 GPIO5 GPIO4 GPIO2 GPIO3 RESET GND WAKE INT SDO SDI SCK CS VDD GND NC GND GND CLKOUT LPOSC2 LPOSC1 RXIP RXQP VDD VDD OSC2 OSC1 VDD GND VDD NC VDD LCAP
Legend: A = Analog, D = Digital, I = Input, O = Output
(c) 2006 Microchip Technology Inc.
Advance Information
DS39776A-page 5
MRF24J40
NOTES:
DS39776A-page 6
Advance Information
(c) 2006 Microchip Technology Inc.
MRF24J40
2.0
2.1
EXTERNAL CONNECTIONS
Oscillator
2.2
Oscillator Start-up
The MRF24J40 is designed to operate at 20 MHz with a crystal connected to the OSC1 and OSC2 pins. A typical oscillator circuit is shown in Figure 2-1.
FIGURE 2-1:
CRYSTAL OSCILLATOR OPERATION
OSC1
The MRF24J40 PHY has an internal PLL that must lock before the device is capable of transmitting or receiving packets. After a full Power-on Reset, the device requires 2 ms to lock. During this delay, all registers and buffer memory may still be read and written to through the SPI bus. However, software should not attempt to transmit any packets (set the TXRTS (TXNMTRIG<0>)), or access any MAC or PHY registers during this period.
2.3
To Internal Logic
CLKOUT Pin
C1 XTAL RS(1) C2 Note 1: OSC2
MRF24J40
A series resistor (RS) may be required for AT strip cut crystals.
The clock out pin is provided to the system designer for use as the host controller clock or as a clock source for other devices in the system. The CLKOUT has an internal prescaler which can divide the output by 1, 2, 4 or 8. The CLKOUT function is enabled via the CLKCTRL register (Register 2-1) and the prescaler is selected via the RFCTRL7 register (Register 2-2).
REGISTER 2-1:
R/W-0 r bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6 bit 5
CLKCTRL: DIVIDED SLEEP CLOCK (50 kHz) SELECTION REGISTER
U-0 -- R/W-0 CLKOEN R/W-0 R/W-0 R/W-0 SCLKDIV<4:0> bit 0 R/W-0 R/W-0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Reserved: Maintain as `0' Unimplemented: Read as `0' CLKOEN: 20 MHz Clock Output Enable bit 1 = Disable 0 = Enable SCLKDIV4:SCLKDIV0: Divided SLPCLK Selection bits Divided by 2n.
bit 4-0
(c) 2006 Microchip Technology Inc.
Advance Information
DS39776A-page 7
MRF24J40
REGISTER 2-2:
R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
RFCTRL7: RF CONTROL REGISTER 7
R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 R/W-0 bit 0
SLPCLK<7:6>
CLKDIV<1:0>
SLPCLK7:SLPCLK6: Sleep Clock Selection bits 00 = None 01 = External crystal 10 = Internal ring oscillator 11 = Reserved Unimplemented: Read as `0' CLKDIV1:CLKDIV0: MRF24J40 Clock Output Frequency bits 00 = 2.5 MHz 01 = 5 MHz 10 = 10 MHz 11 = 20 MHz
bit 5-2 bit 1-0
To create a clean clock signal, the CLKOUT pin is held low for a period when power is first applied. After the Power-on Reset ends, the Oscillator Start-up Timer (OST) will begin counting. When the OST expires, the CLKOUT pin will begin outputting its default frequency of 2.5 MHz (main clock divided by 8).
2.4
RF Output
RFP and RFN are the differential RF input/output pins. These pins are connected to the antenna of the system, as seen in the example circuit diagram in Figure A-1. L5 is an RF choke. This inductor filters out non 2.4 GHz voltages. L3, L4, C37 and C43 act as a balun. The balun converts a differential unbalanced input and converts it to a balanced singled-ended output and visa versa. L1, C23 and C38 form a pi-type matching circuit to match the impedance of the balun to the impedance of the antenna. This circuit is not required if the impedance of the balun matches the antenna impedance. Refer to Appendix A.1 "Layout Considerations and RF Measurements" for more details about board layout and part selection concerning the RF output pins.
DS39776A-page 8
Advance Information
(c) 2006 Microchip Technology Inc.
MRF24J40
3.0 MEMORY ORGANIZATION
All memory in the MRF24J40 is implemented as static RAM. There are five types of memory in the MRF24J40: * * * * * Short Address Control Registers Long Address Control Registers Transmit Buffers Receive Buffers Security Buffer The security buffer provides an engine for the MRF24J40 MAC, which is compatible with the IEEE 802.15.4 LR-WPAN (ZigBee). The security buffer contains the following features: * Transmit encryption and receive decryption. * Seven-mode security suite. * 64 x 8-bit security RAM for security suite storing; one receive key and three transmit keys for TX FIFOs. Beacon FIFO and GTS2 FIFO share the same key space since they will not conflict with each other. Normal FIFO and GTS1 FIFO both have their own transmit key. * Security of APL and NWK layers can be achieved using the same engine. The upper layer security function is compliant to the ZigBee V1.0 and ZigBee 2006 specifications. The SPI interface used to write and read these registers is described in Section 4.0 "Serial Peripheral Interface (SPI)". Figure 3-1 shows the data memory organization for the MRF24J40.
The control registers, both long and short, are used for configuration, control, and status retrieval of the MRF24J40. The control registers are directly read and written to by the SPI interface. The transmit and receive buffers contain transmit and receive memory used by the controller to transmit and receive data.
FIGURE 3-1:
MRF24J40 MEMORY SPACE
Short Address Space
00h Short Address Control Registers 3Fh Transmit Buffers 000h TXN FIFO 07Fh 080h TXB FIFO 0FFh 100h GTS1 FIFO 17Fh 180h GTS2 FIFO 1FFh 200h Control Registers 27Fh 280h Security 2BEh 2BFh Unimplemented 2FFh 300h Receive FIFO 38Fh RX FIFO Security Buffer Long Address Control Registers
Long Address Space
(c) 2006 Microchip Technology Inc.
Advance Information
DS39776A-page 9
MRF24J40
3.1 Control Registers
The control registers provide the main interface between the host controller and the on-chip RF controller logic. Writing to these registers controls the operation of the interface, while reading the registers allows the host controller to monitor operations. The control register memory is partitioned into the short address control register section and the long address control register section. All reserved registers may be read but their contents must not be changed. When reading and writing to registers which contain reserved bits, any rules stated in the register definition should be observed.
FIGURE 3-2:
00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh
MRF24J40 SHORT ADDRESS CONTROL REGISTER MAPPING
RXMCR PANIDL PANIDH SADRL SADRH EADR0 EADR1 EADR2 EADR3 EADR4 EADR5 EADR6 EADR7 RXFLUSH -- -- 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh -- -- -- -- -- -- -- -- -- -- -- TXNMTRIG -- -- -- -- 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh -- -- -- -- TXSR -- -- -- -- -- -- -- -- -- -- -- 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh -- ISRSTS INTMSK GPIO TRISGPIO -- RFCTL -- -- -- BBREG2 -- -- -- BBREG6 RSSITHCCA
FIGURE 3-3:
200h 201h 202h 203h 204h 205h 206h 207h 208h 209h 20Ah 20Bh 20Ch 20Dh 20Eh 20Fh RFCTRL0 -- RFCTRL2 RFCTRL3 -- -- RFCTRL6 RFCTRL7 RFCTRL8 -- -- -- -- -- -- --
MRF24J40 LONG ADDRESS CONTROL REGISTER MAPPING
210h 211h 212h 213h 214h 215h 216h 217h 218h 219h 21Ah 21Bh 21Ch 21Dh 21Eh 21Fh -- CLKINTCR -- -- -- -- -- -- -- -- -- -- -- -- -- -- 220h 221h 222h 223h 224h 225h 226h 227h 228h 229h 22Ah 22Bh 22Ch 22Dh 22Eh 22Fh CLKCTRL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 230h 231h 232h 233h 234h 235h 236h 237h 238h 239h 23Ah 23Bh 23Ch 23Dh 23Eh 23Fh -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 240h 241h 242h 243h 244h 245h 246h 247h 248h 249h 24Ah 24Bh 24Ch -- -- -- -- -- -- -- -- -- -- -- -- --
DS39776A-page 10
Advance Information
(c) 2006 Microchip Technology Inc.
MRF24J40
3.2 MRF24J40 Address Summary
REGISTER FILE SHORT ADDRESS SUMMARY
Bit 7 TXCRCEN Bit 6 BBLPBK Bit 5 ACKEN Bit 4 MACLPBK Bit 3 PANCOORD Bit 2 COORD Bit 1 RXCRCEN Bit 0 PROMI Value on POR 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 DATAONLY ACKREQ r GTS2TXIF BCNONLY SECEN r GTS1TXIF RXFLUSH -000 0000 TXRTS r TXIF TXMSK GPIO0 ---0 0000 0000 0000 0000 0000 1111 1111 --00 0000 Details on page: 21 26 26 27 27 26 26 26 26 26 26 26 26 34 30 31 36 37 39 40 24 25 25 23
TABLE 3-1:
File Name RXMCR PANIDL PANIDH SADRL SADRH EADR0 EADR1 EADR2 EADR3 EADR4 EADR5 EADR6 EADR7 RXFLUSH TXNMTRIG TXSR ISRSTS INTMSK GPIO TRISGPIO RFCTL BBREG2 BBREG6 RSSITHCCA Legend: -- --
MAC PAN Low Byte (PANL<7:0>) MAC PAN High Byte (PANH<15:8>) MAC Short Address Low Byte (SADDRL<7:0>) MAC Short Address High Byte (SADDRH<15:8>) LSB of EUI (EADR0<7:0>) Byte 2 of EUI (EADR1<15:8>) Byte 3 of EUI (EADR2<23:16>) Byte 4 of EUI (EADR3<31:24>) Byte 5 of EUI (EADR4<39:32>) Byte 6 of EUI (EADR5<47:40>) Byte 7 of EUI (EADR6<55:48>) MSB of EUI (EADR7<63:56>) r -- r -- CCAFAIL HSYMTMRIF HSYMTMRMSK GPIO5 TRISGP5 -- RXWRTBLK PENDACK r SECIF SECMSK GPIO4 TRISGP4 r CMDONLY INDIRECT r RXIF RXMSK GPIO3 TRISGP3 r
TXRETRY<7:6> SLPIF SLPMSK -- -- r WAKEIF WAKEMSK -- -- --
GTS2TXMSK GTS1TXMSK GPIO2 TRISGP2 RFRST GPIO1 TRISGP1 r -- r r
TRISGP0 --00 0000 r -- 0--0 0000 0000 00--
CCAMODE<7:6> RSSIREQ RXRSSI r
CCATHRES<5:2> r r
RSSIRDY 0000 0001 0000 0000
RSSITHRES<7:0> - = unimplemented, r = reserved. Shaded cells are unimplemented, read as `0'.
TABLE 3-2:
File Name RFCTRL0 RFCTRL2 RFCTRL3 RFCTRL6 RFCTRL7 RFCTRL8 CLKINTCR CLKCTRL Legend:
REGISTER FILE LONG ADDRESS SUMMARY
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 -- r r Bit 2 -- -- -- r -- RF_VCO -- BATMONEN -- -- -- -- -- -- -- -- INTEDGE Bit 1 -- -- -- -- Bit 0 -- -- -- -- CLKDIV<1:0> SLPCLKOUT SLPCLKEN Value on POR 0000 ---0000 0--0000 0--0-00 0--00-- --00 ---0 ---0 ---- --00 0-00 0000 Details on page: 24 22 22 23 8 23 38 7
CHANNEL<7:4> RFPLL r r TXPOWER<7:3> TXFIL -- r -- -- -- CLKOEN
SLPCLK<7:6> -- -- r -- -- --
SCLKDIV<4:0>
- = unimplemented, r = reserved. Shaded cells are unimplemented, read as `0'.
(c) 2006 Microchip Technology Inc.
Advance Information
DS39776A-page 11
MRF24J40
NOTES:
DS39776A-page 12
Advance Information
(c) 2006 Microchip Technology Inc.
MRF24J40
4.0
4.1
SERIAL PERIPHERAL INTERFACE (SPI)
Overview
The MRF24J40 is designed to interface directly with the Serial Peripheral Interface (SPI) port available on many microcontrollers. The implementation used on this device supports SPI mode 0,0 only. In addition, the SPI port requires that SCK be Idle in a low state; selectable clock polarity is not supported.
Commands and data are sent to the device via the SDI pin, with data being clocked in on the rising edge of SCK. Data is driven out by the MRF24J40 on the SDO line, on the falling edge of SCK. The CS pin must be held low while any operation is performed and returned high when finished. The MRF24J40 accesses the short and long RAM banks in a slightly different manner. The following sections describe the required waveforms in order to read and write from both short and long RAM addresses.
FIGURE 4-1:
SPI INPUT TIMING
CS
SCK
SDI
MSb In
LSb In
SDO
High-Impedance State
FIGURE 4-2:
CS
SPI OUTPUT TIMING
SCK
SDO
MSb Out
LSb Out
SDI
Don't Care
(c) 2006 Microchip Technology Inc.
Advance Information
DS39776A-page 13
MRF24J40
4.2
4.2.1
Short Address Register Interface
READING SHORT ADDRESS REGISTERS
The short address space is accessed by sending a `0' as the first bit of the SPI transfer. The following 6 bits are the address of the target register. The final bit of the first byte is a `0` to indicate that the command is a read. On the next clock edge of SCK, the Most Significant bit of the register will shift out, followed by the rest of the bits.
FIGURE 4-3:
CS
SHORT ADDRESS READ
SCK SDI SDO 0 A5 A4 A3 A2 A1 A0 0 D7 D6 D5 D4 X D3 D2 D1 D0
EXAMPLE 4-1:
SHORT ADDRESS READ EXAMPLE
BYTE GetShortRAMAddress(BYTE address) { BYTE toReturn; CSn = 0; SPIPut((address<<1)&0b01111110); toReturn = SPIGet(); CSn = 1; return toReturn; }
DS39776A-page 14
Advance Information
(c) 2006 Microchip Technology Inc.
MRF24J40
4.2.2 WRITING SHORT ADDRESS REGISTERS
The short address space is accessed by sending a `0' as the first bit of the SPI transfer. The following 6 bits are the address of the target register. The final bit of the first byte is a `1' to indicate that the command is a write. On the next clock edge of SCK, the Most Significant bit of the register will shift out, followed by the rest of the bits.
FIGURE 4-4:
CS
SHORT ADDRESS WRITE
SCK SDI SDO 0 A5 A4 A3 A2 A1 A0 1 D7 D6 D5 D4 D3 X D2 D1 D0
EXAMPLE 4-2:
SHORT ADDRESS WRITE EXAMPLE
void SetShortRAMAddress(BYTE address, BYTE value) { CSn = 0; SPIPut(((address<<1)&0b01111111)|0x01); SPIPut(value); CSn = 1; }
(c) 2006 Microchip Technology Inc.
Advance Information
DS39776A-page 15
MRF24J40
4.3
4.3.1
Long Address Register Interface
READING LONG ADDRESS REGISTERS
The long address space is accessed by sending a `1' as the first bit of the SPI transfer. The following 10 bits are the address of the target register. The final bit is a `0` to indicate that the command is a read. On the next clock edge of SCK, the Most Significant bit of the register will shift out, followed by the rest of the bits.
FIGURE 4-5:
CS SCK SDI SDO 1 A9 A8
LONG ADDRESS READ
A7
A6
A5
A4
A3
A2
A1
A0
0 X D7 D6
X D5 D4 D3 D2 D1 D0
EXAMPLE 4-3:
LONG ADDRESS READ EXAMPLE
BYTE GetLongRAMAddress(WORD address) { BYTE toReturn; CSn = 0; SPIPut(((address>>3)&0b01111111)|0x80); SPIPut(((address<<5)&0b11100000)); toReturn = SPIGet(); CSn = 1; return toReturn; }
DS39776A-page 16
Advance Information
(c) 2006 Microchip Technology Inc.
MRF24J40
4.3.2 WRITING LONG ADDRESS REGISTERS
4.4
Buffer Interface
The long address space is accessed by sending a `1 ` as the first bit of the SPI transfer. The following 10 bits are the address of the target register. The final bit is a `1 ` to indicate that the command is a write. On the next clock edge of SCK, the Most Significant bit of the register will shift out, followed by the rest of the bits.
The receive and transmit buffers in the MRF24J40 are located in the long RAM address space. These buffers are accessed using the same process as accessing the long RAM control addresses. The received buffer is read-only and should not be written to. The use of these buffers is described in Section 7.0 "Transmitting and Receiving Packets".
FIGURE 4-6:
CS SCK SDI SDO 1 A9 A8
LONG ADDRESS WRITE
A7
A6
A5
A4
A3
A2
A1
A0
1
X X
D7
D6
D5
D4
D3
D2
D1
D0
EXAMPLE 4-4:
LONG ADDRESS WRITE EXAMPLE
void SetLongRAMAddress(WORD address, BYTE value) { CSn = 0; SPIPut((((BYTE)(address>>3))&0b01111111)|0x80); SPIPut((((BYTE)(address<<5))&0b11100000)|0x10); SPIPut(value); CSn = 1; }
(c) 2006 Microchip Technology Inc.
Advance Information
DS39776A-page 17
MRF24J40
NOTES:
DS39776A-page 18
Advance Information
(c) 2006 Microchip Technology Inc.
MRF24J40
5.0
5.1
IEEE 802.15.4TM-2003
Overview
5.2
Packet Format
Before discussing the use of the MRF24J40, it may be helpful to review the structure of a typical data frame. Users requiring more information should refer to the IEEE 802.15.4 Standard.
Normal IEEE 802.15.4 compliant packets are between 5 and 127 bytes long. They are made up of several possible fields: destination address information, source address information, a length field, data payload and a Cyclic Redundancy Check (CRC). Additionally, a 4-byte preamble field and Start-of-Frame Delimiter (SFD) byte are appended to the beginning of the packet. Thus, traffic seen on the air will appear as shown in Figure 5-1.
FIGURE 5-1:
PACKET FORMAT
Number of Bytes
Field
Comments
4
Preamble
Filtered out by module Start-of-Frame delimiter - Filtered out by module
1 1 2 1
SFD Packet Length Frame Control Sequence Number Destination Address Information Source Address Information
Used to calculate FCS
0/4/10
Short or long address of the destination device plus the PAN identifier. Length selected in the frame control. Short or long address of the source device plus the PAN identifier. Length selected in the frame control.
0/2/4/8/ 10
0-122 Used to calculate packet length
Data Payload
2
FCS
Frame check sequence - CRC
(c) 2006 Microchip Technology Inc.
Advance Information
DS39776A-page 19
MRF24J40
5.2.1 PREAMBLE/START-OF-FRAME DELIMITER 5.2.6 SOURCE ADDRESS INFORMATION
When transmitting and receiving data with the MRF24J40, the preamble and Start-of-Frame delimiter bytes will automatically be generated or stripped from the packets when they are transmitted or received. The host controller does not need to concern itself with them. Normally, the host controller will also not need to concern itself with the CRC, which the MRF24J40 will also be able to automatically generate when transmitting and verify when receiving. The CRC fields will, however, be written into the receive buffer when packets arrive, so they may be evaluated by the host controller if needed. The source address fields of an IEEE 802.15.4 packet can change depending on the frame control field of that packet. The frame control field can specify that no destination address is present, or can specify that the short address (2 bytes) or long address (8 bytes) is present. The frame control can also specify, by using the intra-PAN bit, that the source PAN matches the destination PAN and is thus, not included in the packet. Long addresses consist of two portions. The first three bytes are known as the Extended Organizationally Unique Identifier (EUI). EUIs are distributed by the IEEE 802.15.4. The last five bytes are address bytes which can contain the needed requirements at the discretion of the company that purchased the EUI. When transmitting packets, the assigned source long or short address, depending on the setting of the frame control field, must be written into the transmit buffer by the host controller. The MRF24J40 will not automatically include the source address information.
5.2.2
LENGTH
The length field is a 1-byte field which defines the size of the packet excluding itself, the preamble and SFD, but including all other bytes of the packet, including FCS.
5.2.3
FRAME CONTROL
The frame control field describes the format of this packet. It defines the type of packet (beacon, data, ACK, etc.) the addressing modes used, if the packet is encrypted or not, if the packet requires an ACK and if the packet is an intra-PAN network. This information is used by the host controller to determine how to decipher the data that follows the frame control field.
5.2.7
DATA
The data section of the packet can vary in length from 0 bytes to 122 bytes. Packets that exceed 127 bytes, including the frame control, source addressing, destination addressing, data and FCS fields, will be filtered out by the MRF24J40.
5.2.4
SEQUENCE NUMBER
5.2.8
FCS
The sequence number field is a 1-byte sequence number that distinguishes packets. The sequence number field is used in the Acknowledgement process. An ACK packet contains no addressing information, so the uniqueness of the sequence number is the sole determining factor for verifying that a packet reached its destination. The MRF24J40 has an Auto-Acknowledgement feature that is described in Section 7.1 "Transmitting Packets".
5.2.5
DESTINATION ADDRESS INFORMATION
The destination address fields of an IEEE 802.15.4 packet can change depending on the frame control field of that packet. The frame control field can specify that no destination address is present, or can specify that the short address (2 bytes) or long address (8 bytes) is present. In all cases where an address is specified, the destination PAN identifier will also be included. On incoming packets, the MRF24J40 will filter out packets that do not match the preconfigured addressing information for that radio. This eliminates any software intervention for packets that do not meet the addressing requirements. When transmitting the host controller is required to write the appropriate destination address into the transmit buffer.
The FCS field is a 2-byte field which contains an industry standard, 16-bit CRC calculated with the data from the frame control, sequence number, destination, source, and data fields. When receiving packets, the MRF24J40 will check the CRC of each incoming packet. If the RXCRCEN bit (RXMCR<1>) is cleared, packets with invalid CRCs will automatically be discarded. If RXCRCEN is set, and the packet meets all other receive filtering criteria, the packet will be written into the receive buffer and the host controller will be able to determine if the CRC was valid by reading the receive status vector (see Section 7.3 "Receiving Packets"). When transmitting packets, the MRF24J40 will automatically generate a valid CRC and transmit it attached to the end of the packet if the TXCRCEN bit (RXMCR<7>) is cleared.
DS39776A-page 20
Advance Information
(c) 2006 Microchip Technology Inc.
MRF24J40
6.0
6.1
INITIALIZATION
Overview
6.2
Receive Filters
Before the MRF24J40 can be used to transmit and receive packets, certain device settings must be initialized. Depending on the application, some configuration options may need to be changed. Normally, these tasks may be accomplished once after Reset and do not need to be changed thereafter.
To minimize the processing requirements of the host controller, the MRF24J40 incorporates several different receive filters which can automatically reject packets which are not needed. These options are controlled through the RXMCR register.
REGISTER 6-1:
R/W-0 TXCRCEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7
RXMCR: RECEIVE FILTER CONTROL REGISTER
R/W-0 r R/W-0 ACKEN R/W-0 r R/W-0 PANCOORD R/W-0 COORD R/W-0 RXCRCEN R/W-0 PROMI bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
TXCRCEN: No CRC Data with Normal FIFO bit 1 = CRC is disabled for the TX FIFO 0 = CRC is enabled for the TX FIFO Reserved: Maintain as `0' ACKEN: No ACK Respond in Any Case bit 1 = ACK response is always disabled 0 = ACK response enabled. ACKs are returned when they are requested. Reserved: Maintain as `0' PANCOORD: PAN Coordinator bit 1 = Set as PAN coordinator 0 = Not set as PAN coordinator COORD: Coordinator bit 1 = Set as coordinator 0 = Not set as coordinator RXCRCEN: Error Report bit 1 = RX all kinds of PKT (including CRC error) 0 = Only RX PKT (CRC ok) PROMI: RX All Kinds of PKT bit (CRC ok) 1 = RX all kinds of PKT (CRC ok) 0 = Discard PKT when there is a MAC address mismatch, illegal frame type, dPAN/sPAN or MAC short address mismatch
bit 6 bit 5
bit 4 bit 3
bit 2
bit 1
bit 0
(c) 2006 Microchip Technology Inc.
Advance Information
DS39776A-page 21
MRF24J40
6.3 PHY Initialization
Note: The physical layer of the MRF24J40 controls the current levels going to different sections of the device, as well as thresholds and controls used in packet reception and transmission. There are several registers that may require modification in order to operate in the application's intended mode. The RSSI threshold defaults to `0', however, it can be set to a user-defined RSSI threshold limit. Please note, any RSSI value resulting from a CCA request that is below the RSSI threshold limit will result in a failure.
REGISTER 6-2:
R/W-0 RFPLL bit 7 Legend: R = Readable bit -n = Value at POR bit 7
(1)
RFCTRL2: RF CONTROL REGISTER 2
R/W-0 r R/W-0 r R/W-0 r R/W-0 r U-0 -- U-0 -- U-0 -- bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
RFPLL: RF-PLL Control bit(1) 1 = PLL enabled 0 = PLL disabled Reserved: Maintain as `0' Unimplemented: Read as `0' PLL must be enabled for RF reception or transmission.
bit 6-3 bit 2-0 Note 1:
REGISTER 6-3:
R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-3
RFCTRL3: RF CONTROL REGISTER 3
R/W-0 R/W-0 TXPOWER<7:3> R/W-0 R/W-0 U-0 -- U-0 -- U-0 -- bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
TXPOWER7:TXPOWER3: Small Scale Control for TX Power in dB bits 00000 = 0 dB 00001 = -1.25 dB 00010 = -2.5 dB 00011 = -3.75 dB 00100 = -5 dB 00101 = -6.25 dB 00110 = -7.5 dB 00111 = -8.75 dB ... 11111 = -38.75 dB Unimplemented: Read as `0'
bit 2-0
DS39776A-page 22
Advance Information
(c) 2006 Microchip Technology Inc.
MRF24J40
REGISTER 6-4:
R/W-0 TXFIL bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6 bit 5-4 bit 3 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
RFCTRL6: RF CONTROL REGISTER 6
U-0 -- R/W-0 r R/W-0 r R/W-0 BATMONEN U-0 -- U-0 -- U-0 -- bit 0
TXFIL: TX Filter Control bit Recommended value: `1'. Unimplemented: Read as `0' Reserved: Maintain as `0' BATMONEN: Battery Monitor Enable bit 1 = Enabled 0 = Disabled Unimplemented: Read as `0'
bit 2-0
REGISTER 6-5:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4
RFCTRL8: RF CONTROL REGISTER 8
U-0 -- U-0 -- R/W-0 RF_VCO U-0 -- U-0 -- U-0 -- R/W-0 SLPCLKOUT bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' RF_VCO: VCO Control bit 1 = Enhanced VCO (recommended) 0 = Normal VCO Unimplemented: Read as `0' SLPCLKOUT: 20 MHz Reference Output Clock Source bit 1 = Stabilize CLKOUT while recovering from Sleep 0 = Stabilize CLKOUT after a wake from Sleep
bit 3-1 bit 0
REGISTER 6-6:
R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0
RSSITHCCA: RSSI THRESHOLD FOR CCA REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 0
RSSITHRES<7:0>
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
RSSITHRES7:RSSITHRES0: RSSI Threshold for CCA/ED Mode bits
(c) 2006 Microchip Technology Inc.
Advance Information
DS39776A-page 23
MRF24J40
6.4 MAC Initialization
6.4.2 CHANNEL SELECTION
The medium access control layer of the MRF24J40 consists of several registers that define how this device operates on an IEEE 802.15.4 network. The operational channel is selected using the RFCTRL0 register.
6.4.1
DEVICE CONFIGURATION
The RXMCR, described in Section 6.2 "Receive Filters", should be set to the appropriate value for the intended device operation. If the device is operating as a PAN coordinator, the PANCOORD bit should be set. If the device is operating as a coordinator, then the COORD bit should be set.
REGISTER 6-7:
R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-4
RFCTRL0: RF CONTROL REGISTER 0
R/W-0 R/W-0 R/W-0 U-0 -- U-0 -- U-0 -- U-0 -- bit 0
CHANNEL<7:4>
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
CHANNEL7:CHANNEL4: Channel Number bits 00000 = Channel 11 00001 = Channel 12 00010 = Channel 13 ... 11111 = Channel 26 Unimplemented: Read as `0'
bit 3-0
REGISTER 6-8:
W-0 r bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6-5 bit 4-3 bit 2
RFCTL: RF MODE CONTROL REGISTER
U-0 -- U-0 -- R/W-0 r R/W-0 r R/W-0 RFRST R/W-0 r R/W-0 r bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Reserved: Maintain as `0' Unimplemented: Read as `0' Reserved: Maintain as `0' RFRST: RF Reset bit 1 = Reset RF (turn off RF) 0 = Normal operation Reserved: Maintain as `0'
bit 1-0
DS39776A-page 24
Advance Information
(c) 2006 Microchip Technology Inc.
MRF24J40
REGISTER 6-9:
R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
BBREG2: BASEBAND CCA/RSSI MODE REGISTER 2
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 -- U-0 -- bit 0
CCAMODE<7:6>
CCATHRES<5:2>
CCAMODE7:CCAMODE6: CCA Mode bits 00 = Reserved 01 = CCA Mode 1, carrier sense only 10 = CCA Mode 2, energy above threshold 11 = CCA Mode 3, carrier sense with energy above threshold CCATHRES5:CCATHRES2: CCA Carrier Sense Threshold bits CCA/CS value set to 0xE or `1110'. Unimplemented: Read as `0'
bit 5-2 bit 1-0
REGISTER 6-10:
R/W-0 RSSIREQ bit 7 Legend: R = Readable bit -n = Value at POR bit 7
BBREG6: BASEBAND RSSI MODE REGISTER 6
R/W-0 r R/W-0 r R/W-0 r R/W-0 r R/W-0 r R-1 RSSIRDY bit 0
R/W-0 RXRSSI
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
RSSIREQ: RSSI Mode 1 bit 1 = Initiate an RSSI calculation (write back to `0' when complete) 0 = Otherwise RXRSSI: RSSI Mode 2 bit 1 = Calculating RSSI for RX packet 0 = No calculating RSSI for RX packet Reserved: Maintain as `0' RSSIRDY: RSSI Ready Signal Firmware Request bit 1 = RSSI value ready 0 = Otherwise
bit 6
bit 5-1 bit 0
(c) 2006 Microchip Technology Inc.
Advance Information
DS39776A-page 25
MRF24J40
6.4.3 LONG ADDRESSES
Every device in the world has a unique long address. Long addresses are described in more detail in Section 5.2.5 "Destination Address Information" and Section 5.2.6 "Source Address Information". EADR0-EADR7 are eight short RAM address registers in the MRF24J40 that are used to define the device's long address. These addresses should be loaded into the device during the device configuration. The MRF24J40 will automatically filter out any long address packets that do not match the contents of EADR0-EADR7. located in the short RAM address space. The MRF24J40 automatically filters out packets that are specified as short address destinations with addresses that do not match these registers. The exception to this rule is packets with the broadcast short address (FFFFh) and/or the broadcast PAN ID (FFFFh). Packets that match the short address and have the broadcast PAN ID will be accepted, as well as packets with the broadcast short address that match the PAN ID. A true broadcast packet will have both the short address and PAN ID set to the broadcast address. The MRF24J40 will also receive these packets no matter what the setting of the short address and PAN ID registers. Example 6-1 shows how to initialize the MRF24J40.
6.4.4
SHORT ADDRESS AND PAN ID
The device's short address and PAN ID are programmed into the MRF24J40 through the SADRL, SADRH, PANIDL and PANIDH registers. These registers are
REGISTER 6-11:
R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0
PANIDL: MAC PAN LOW BYTE REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 0
MAC PAN Low Byte (PANL<7:0>)
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
PANL7:PANL0: Lower Byte of PAN Address bits
REGISTER 6-12:
R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0
PANIDH: MAC PAN HIGH BYTE REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 0
MAC PAN High Byte (PANH<15:8>)
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
PANH15:PANH8: Higher Byte of PAN Address bits
DS39776A-page 26
Advance Information
(c) 2006 Microchip Technology Inc.
MRF24J40
REGISTER 6-13:
R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
SADRL: MAC SHORT ADDRESS LOW BYTE REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 0
MAC Short Address Low Byte (SADDRL<7:0>)
SADDRL7:SADDRL0: Lower Byte of Short Address bits
REGISTER 6-14:
R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0
SADRH: MAC SHORT ADDRESS HIGH BYTE REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 0
MAC Short Address High Byte (SADDRH<15:8>)
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
SADDRH15:SADDRH8: Higher Byte of Short Address bits
(c) 2006 Microchip Technology Inc.
Advance Information
DS39776A-page 27
MRF24J40
EXAMPLE 6-1: INITIALIZING THE MRF24J40
void MRF24J40Init(void) { BYTE i; WORD j; /* place the device in hardware reset */ RESETn = 0; for(j=0;j<(WORD)300;j++){} /* remove the device from hardware reset */ RESETn = 1; for(j=0;j<(WORD)300;j++){} /* reset the RF module */ SetShortRAMAddr(RFCTL,0x04); /* remove the RF module from reset */ SetShortRAMAddr(RFCTL,0x00); /* flush the RX fifo */ SetShortRAMAddr(WRITE_RXFLUSH,0x01); /* Program the short MAC Address, 0xffff */ SetShortRAMAddr(SADRL,0xFF); SetShortRAMAddr(SADRH,0xFF); SetShortRAMAddr(PANIDL,0xFF); SetShortRAMAddr(PANIDH,0xFF); /* Program Long MAC Address*/ for(i=0;i<(BYTE)8;i++) { SetShortRAMAddr(EADR0+i*2,myLongAddress[i]); } /* enable the RF-PLL */ SetLongRAMAddr(RFCTRL2,0x80); /* set TX for max output power */ SetLongRAMAddr(RFCTRL3,0x00); /* enabled TX filter control */ SetLongRAMAddr(RFCTRL6,0x80); SetLongRAMAddr(RFCTRL8,0b00010000); /* Program CCA mode using RSSI */ SetShortRAMAddr(BBREG2,0x78); /* Enable the packet RSSI */ SetShortRAMAddr(BBREG6,0x40); /* Program CCA, RSSI threshold values */ SetShortRAMAddr(RSSITHCCA,0x00); SetLongRAMAddr(RFCTRL0,0x00); //channel 11 SetShortRAMAddr(RFCTL,0x04); SetShortRAMAddr(RFCTL,0x00); } //reset the RF module with new settings
DS39776A-page 28
Advance Information
(c) 2006 Microchip Technology Inc.
MRF24J40
7.0
7.1
TRANSMITTING AND RECEIVING PACKETS
Transmitting Packets
7.2
TX FIFO Format
The TX MAC performs three major tasks conforming to IEEE 802.15.4: * TX FIFO Control * Automatic CSMA-CA and Timing Alignments * Hardware Superframe Handling For TX FIFO control function, TX MAC controls 4 FIFOs, including beacon, normal and 2 GTS FIFOs. When each FIFO is triggered, TX MAC performs a CSMA-CA algorithm, sends a packet to the Transmit Baseband (TXBB) at the right time, handles the retransmission if an ACK is required but not received and generates FCS bytes automatically. The automatic CSMA-CA algorithm performs timing alignments, such as LIFS, SIFS and ACK turnaround time. The user can simply program parameters for the CSMA-CA algorithm. The TX MAC will perform automatically according these parameters. For hardware superframe handling, TX MAC builds up the timing frame of a superframe. It includes CAP, CFP, INACTIVE and each time slot. TX MAC sends beacon, normal and GTS FIFOs at the right time, automatically, at each transmission. This largely reduces the complexity of the Beacon Enable mode of IEEE 802.15.4.
The MAC inside the MRF24J40 will automatically generate the preamble and Start-of-Frame delimiter fields when transmitting. Additionally, the MAC can generate any padding (if needed), and the CRC, if configured to do so. The host controller must generate and write all other frame fields into the buffer memory for transmission. Before transmitting packets, the MAC registers, which alter the transmission characteristics, should be initialized as documented in Section 6.0 "Initialization".
FIGURE 7-1:
Address
TRANSMIT PACKET LAYOUT Memory Description
0x000 0x001 0x002-0x003 0x004 0x005
Header Length Packet Length (m + 3) Frame Control Sequence Number Data[0] Data[...]
Length of the header. This field is described in more detail in the security section of this document. The length of the packet, not including the length or FCS. The frame control field describing how this packet should behave. The sequence number distinguishing this packet.
The destination and source addressing information, as well as any application data.
0x005 + (m - 1) 0x006 + m 0x007 + m
Data[m - 1] FCS[0] The CRC value for the packet; written by hardware. FCS[1]
(c) 2006 Microchip Technology Inc.
Advance Information
DS39776A-page 29
MRF24J40
7.2.1 TRIGGER PACKET TRANSMISSION
The MRF24J40 handles the Clear Channel Assessment (CCA) and Carrier Sense Multiple Access Collision Avoidance (CSMA-CA) algorithms in hardware. The MRF24J40 also handles automatic retransmission of packets that require an ACK. If the frame control field of the packet requires an ACK, the ACKREQ bit (TXNMTRIG<2>) needs to be set before transmission. Once the TX FIFO is loaded with the data to transmit the TXRTS bit (TXNMTRIG<0>) is used to transmit the packet.
REGISTER 7-1:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4
TXNMTRIG: TRIGGER AND SETTING FOR NORMAL FRAME (CAP) REGISTER
U-0 -- U-0 -- R-0 PENDACK R/W-0 INDIRECT
(1)
R/W-0 ACKREQ
(1)
R/W-0 SECEN
(1)
W-0 TXRTS bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' PENDACK: Data Pending Status in ACK bit Status of the data pending bit in ACK from previous transmission. This bit is reset by hardware on the next transmission. 1 = Data pending bit was set 0 = Data pending bit was cleared INDIRECT: Activate Indirect Transmission bit(1) 1 = Indirect transmission enabled 0 = Indirect transmission disabled ACKREQ: TX Packet in TXN FIFO needs ACK Response bit(1) 1 = ACK requested 0 = No ACK requested SECEN: Secure Current TX Packet bit(1) 1 = Secure packet 0 = Send packet without securing it TXRTS: Trigger TX MAC to Send the Packet in TX FIFO bit 1 = Send the packet in the TX FIFO, automatically cleared by hardware This bit is cleared at the next triggering of TXN FIFO.
bit 3
bit 2
bit 1
bit 0
Note 1:
DS39776A-page 30
Advance Information
(c) 2006 Microchip Technology Inc.
MRF24J40
7.2.2 TRANSMISSION STATUS
When a transmission completes, the TXIF flag of the ISRSTS register will become set. Once the TXIF bit is set, the status of the transmission is located in the TXSR register.
REGISTER 7-2:
R-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5
TXSR: TX MAC STATUS REGISTER
R-0 R-0 CCAFAIL R-0 r R-0 r R-0 r R-0 r R-0 r bit 0
TXRETRY<7:6>
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
TXRETRY7:TXRETRY6: Retry Times bits Defines the retry times of the most recent TXN FIFO transmission. CCAFAIL: Clear Channel Assessment (CCA) Status of Last Transmission bit 1 = CCA failed 0 = CCA passed Reserved: Maintain as `0'
bit 4-0
7.3
Receiving Packets
The following section details the reception of a non-secured frame. When the MRF24J40 receives a packet that passes the MAC layer addressing, threshold and packet type filters, it will indicate the reception of this packet to the host controller by setting the RXIF bit (ISRSTS<3>). The packet will remain in the buffer until the host frees the buffer. No other packets can be received while the buffer is holding a packet.
The behavior of RX FIFO follows a certain rule. When a received packet is not filtered or dropped, a received interrupt/status will be issued. The interrupt is read-to-clear to save host operation time. However, the RX FIFO is flushed only using the following three methods: * The host reads the first byte and the last byte to the packet * The host issues RX flush * A software is reset For RX filter function, the Promiscuous mode is supported to receive all FCS-ok packets. An Error mode is supported to receive all packets that successfully correlated PHY level preamble and delimiter.
7.4
RX MAC
The RX MAC block will do CRC checking, parse the received frame type and address recognition, then store the received frame into RX FIFO. In addition to the IEEE 802.15.4 packet, there are also 2 bytes of information that are appended to the end of the packet after the FCS field: LQI and RSSI.
(c) 2006 Microchip Technology Inc.
Advance Information
DS39776A-page 31
FIGURE 7-2:
RECEIVE PROCESS
DS39776A-page 32
RXMCR.PROMI = 1? YES Accept Packet NO Long address destination? YES NO Reject Packet NO YES Matches EADR0EADR7? Short address destination? YES RXFLUSH.DATA only = 1? YES NO NO NO Matches SADRH, SADRL, PANIDH, PANIDL or 0xFFFF? YES Data packet? NO Reject Packet YES Reject Packet RXFLUSH.BCN only = 1? NO YES Beacon packet? NO Reject Packet YES RXFLUSH.CMD only = 1? NO Accept Packet YES Command packet? NO Reject Packet YES Accept Packet
Packet Received Over the Air, RXIF = 1
MRF24J40
RXMCR.RXCRCEN N = 1?
YES
NO
YES
CRC valid?
NO
Advance Information
Reject Packet
(c) 2006 Microchip Technology Inc.
MRF24J40
7.4.1 RECEIVE PACKET LAYOUT
When a packet passes all of the enabled filters, it is placed in the receive FIFO in the following format.
FIGURE 7-3:
Address
RECEIVE PACKET LAYOUT.
Memory
Description
0x300 0x301-0x302 0x303 0x304
Packet Length (m + 5) Frame Control Sequence Number Data[0] Data[...]
The length of the packet, not including the packet length, but does include the FCS. The frame control field describing how this packet should behave. The sequence number distinguishing this packet.
The destination and source addressing information as well as any application data.
0x304 + (m - 1) 0x305 + m 0x306 + m 0x307 + m 0x308 + m
Data[m - 1] FCS[0] The CRC value for the packet; written by hardware. FCS[1] LQI RSSI The link quality index of the received packet. The received signal strength indicator for the received packet.
(c) 2006 Microchip Technology Inc.
Advance Information
DS39776A-page 33
MRF24J40
7.4.2 FREEING RECEIVE BUFFER SPACE
The RX buffer is cleared when the length byte of the packet and the last byte of the FCS are read. Once both of these values are read from the RX buffer, the buffer will enable itself to receive another packet. Because the LQI and RSSI values are appended to the end of the packet after the FCS, it may be advisable to read these values out of the RX buffer before reading the FCS. Alternatively, it is possible to clear the RX buffer by flushing it. This is done through the RXFLUSH register.
REGISTER 7-3:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6-5 bit 4
RXFLUSH: RECEIVE FIFO FLUSH REGISTER
R/W-0 r R/W-0 r R/W-0 R/W-0 R/W-0 DATAONLY R/W-0 BCNONLY W-0 RXFLUSH bit 0
RXWRTBLK CMDONLY
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' Reserved: Maintain as `0' RXWRTBLK: Software Write to RX FIFO Address bit 1 = Writing to any RX FIFO address is enabled 0 = Writing to any RX FIFO address is disabled CMDONLY: Command Packet Receive bit 1 = Only command packets are received, all other packets are filtered out 0 = All valid packets are received DATAONLY: Data Packet Receive bit 1 = Only data packets are received, all other packets are filtered out 0 = All valid packets are received BCNONLY: Beacon Packet Receive bit 1 = Only beacon packets are received, all other packets are filtered out 0 = All valid packets are received RXFLUSH: Flush RX FIFO Address bit 1 = Flush the RX FIFO. Cleared by hardware. 0 = Previous flush complete
bit 3
bit 2
bit 1
bit 0
7.5
Transceiver
The MRF24J40 receiver features a low IF architecture and consists of an LNA, a pair of down conversion mixers, polyphase channel filters, baseband limiter amplifiers and RSSI technology. An ADC is used to sample the RSSI value and the sampled data is stored in a register from which the data can be read out via the SPI bus. The local oscillator generation circuits (VCO, PLL and buffers) are shared with the receiver and
transmitter. The Low Noise Amplifier (LNA) features a differential input for high performance. The RX/TX switch is integrated and LNA input and Power Amplifier (PA) output share the same pins. A common external matching network and single-ended to differential conversion is required. The transmitter features a direct conversion architecture and has a 0 to -38.75 dBm output power. The output power adjustment is in 1.25 dB step. The TX gain is programmed by the SPI bus.
DS39776A-page 34
Advance Information
(c) 2006 Microchip Technology Inc.
MRF24J40
8.0 INTERRUPTS
8.1 Interrupt Structure
The MRF24J40 has a simple interrupt structure. There is one interrupt pin that signals all of the possible events. The ISRSTS register is a read-to-clear register that specifies which interrupt(s) caused the interrupt. The INTMSK register is used to block unwanted interrupt sources from generating interrupts. The INTEDGE bit (CLKINTCR<1>) controls the polarity of the interrupt pin. Once ISRSTS is read by the host controller, the interrupt flags are cleared. The host controller should make certain to handle all returned flags each time the ISRSTS register is read. When an enabled interrupt occurs, the interrupt pin will remain at its interrupt state, as determined by the INTEDGE bit, until all of the flags which are causing the interrupt are cleared or masked off (the mask bits are set) by the host controller. If more than one interrupt source is enabled, the host controller must poll each flag in the ISRSTS register to determine the source(s) of the interrupt.
FIGURE 8-1:
MRF24J40 INTERRUPT LOGIC
ISRSTS.SLPIF INTMSK.SLPMSK
ISRSTS.WAKEIF INTMSK.WAKEMSK
ISRSTS.HSYMTMRIF INTMSK.HSYMTMRMSK CLKINTCR.INTEDGE ISRSTS.SECIF INTMSK.SECMSK INT ISRSTS.RXIF INTMSK.RXMSK
ISRSTS.GTS2TXIF INTMSK.GTS2TXMSK
ISRSTS.GTS1TXIF INTMSK.GTS1TXMSK
ISRSTS.TXIF INTMSK.TXMSK
(c) 2006 Microchip Technology Inc.
Advance Information
DS39776A-page 35
MRF24J40
8.1.1 INT INTERRUPT STATUS REGISTERS
The registers associated with the INT interrupts are shown in Register 8-1, Register 8-2 and Register 8-3.
REGISTER 8-1:
RC-0 SLPIF bit 7 Legend: R = Readable bit -n = Value at POR bit 7
ISRSTS: INTERRUPT STATUS REGISTER
RC-0 WAKEIF RC-0 HSYMTMRIF RC-0 SECIF RC-0 RXIF RC-0 GTS2TXIF RC-0 GTS1TXIF RC-0 TXIF bit 0 RC = Read to clear W = Writable bit `1' = Bit is set SLPIF: Sleep Alert Interrupt bit 1 = Sleep alert interrupt occurred 0 = Otherwise WAKEIF: Wake-up Alert Interrupt bit 1 = Wake-up interrupt occurred 0 = Otherwise HSYMTMRIF: Half Symbol Timer Interrupt bit 1 = Half symbol timer interrupt occurred 0 = Otherwise SECIF: Security Key Request Interrupt bit 1 = Security key request interrupt occurred 0 = Otherwise RXIF: RX OK Interrupt bit 1 = RX OK interrupt occurred 0 = Otherwise GTS2TXIF: GTS FIFO 2 Release Interrupt bit 1 = GTS2 transmission interrupt occurred 0 = Otherwise GTS1TXIF: GTS FIFO 1 Release Interrupt bit 1 = GTS1 transmission interrupt occurred 0 = Otherwise TXIF: TX FIFO Release Interrupt bit 1 = TX FIFO transmission interrupt occurred 0 = Otherwise U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS39776A-page 36
Advance Information
(c) 2006 Microchip Technology Inc.
MRF24J40
REGISTER 8-2:
R/W-1 SLPMSK bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
INTMSK: INTERRUPT MASK REGISTER
R/W-1 R/W-1 R/W-1 SECMSK R/W-1 RXMSK R/W-1 R/W-1 R/W-1 TXMSK bit 0
WAKEMSK HSYMTMRMSK
GTS2TXMSK GTS1TXMSK
SLPMSK: Sleep Alert Mask bit 0 = Enable Sleep interrupt 1 = Otherwise WAKEMSK: Wake-up Alert Mask bit 0 = Enable Wake interrupt 1 = Otherwise HSYMTMRMSK: Half Symbol Timer Mask bit 0 = Enable half symbol timer interrupt 1 = Otherwise SECMSK: Security Interrupt Mask bit 0 = Enable security interrupt 1 = Otherwise RXMSK: RX OK Mask bit 0 = Enable receive interrupt 1 = Otherwise GTS2TXMSK: GTS FIFO 2 IRQ Mask bit 0 = Enable GTS FIFO 2 transmit interrupt 1 = Otherwise GTS1TXMSK: GTS FIFO 1 IRQ Mask bit 0 = Enable GTS FIFO 1 transmit interrupt 1 = Otherwise TXMSK: TX Normal FIFO IRQ Mask bit 0 = Enable normal FIFO transmit interrupt 1 = Otherwise
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
(c) 2006 Microchip Technology Inc.
Advance Information
DS39776A-page 37
MRF24J40
REGISTER 8-3:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-2 bit 1 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
CLKINTCR: SLPCLK ON/OFF AND INTERRUPT POLARITY REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 INTEDGE R/W-0 SLPCLKEN bit 0
Unimplemented: Read as `0' INTEDGE: Interrupt Edge Polarity bit 1 = Rising edge 0 = Falling edge SLPCLKEN: Sleep Clock Enable bit 1 = Disabled 0 = Enabled
bit 0
DS39776A-page 38
Advance Information
(c) 2006 Microchip Technology Inc.
MRF24J40
9.0
9.1
GENERAL PURPOSE I/O
GPIO Registers
The MRF24J40 has 6 available, general purpose I/O pins. These pins are interfaced through the GPIO and TRISGPIO registers.
REGISTER 9-1:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
GPIO: GPIO PORT REGISTER
U-0 -- R/W-0 GPIO5 R/W-0 GPIO4 R/W-0 GPIO3 R/W-0 GPIO2 R/W-0 GPIO1 R/W-0 GPIO0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' GPIO5: General Purpose I/O GPIO5 bit GPIO4: General Purpose I/O GPIO4 bit GPIO3: General Purpose I/O GPIO3 bit GPIO2: General Purpose I/O GPIO2 bit GPIO1: General Purpose I/O GPIO1 bit GPIO0: General Purpose I/O GPIO0 bit
EXAMPLE 9-1:
READ/WRITE EXAMPLE
//set GPIO5-2 to output, and GPIO 1-0 as input //set GPIO0 high and GPIO1 as low.
SetShortAddress(TRISGPIO,0x03); SetShortAddress(GPIO,0x01);
(c) 2006 Microchip Technology Inc.
Advance Information
DS39776A-page 39
MRF24J40
REGISTER 9-2:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
TRISGPIO: GPIO PIN DIRECTION AND SPI MODE REGISTER
U-0 -- R/W-0 TRISGP5 R/W-0 TRISGP4 R/W-0 TRISGP3 R/W-0 TRISGP2 R/W-0 TRISGP1 R/W-0 TRISGP0 bit 0
Unimplemented: Read as `0' TRISGP5: General Purpose I/O GPIO5 Direction bit 1 = Output 0 = Input TRISGP4: General Purpose I/O GPIO4 Direction bit 1 = Output 0 = Input TRISGP3: General Purpose I/O GPIO3 Direction bit 1 = Output 0 = Input TRISGP2: General Purpose I/O GPIO2 Direction bit 1 = Output 0 = Input TRISGP1: General Purpose I/O GPIO1 Direction bit 1 = Output 0 = Input TRISGP0: General Purpose I/O GPIO0 Direction bit 1 = Output 0 = Input
bit 4
bit 3
bit 2
bit 1
bit 0
DS39776A-page 40
Advance Information
(c) 2006 Microchip Technology Inc.
MRF24J40
10.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings()
Ambient temperature under bias.............................................................................................................. -40C to +85C Storage temperature .............................................................................................................................. -65C to +150C Voltage on any combined digital and analog pin with respect to VSS (except VDD)........................ -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ............................................................................................................ -0.3V to 3.6V Total power dissipation (Note 1) ...............................................................................................................................1.0W Maximum output current sunk by GPIO1-GPIO5 pins ..............................................................................................1 mA Maximum output current sourced by GPIO1-GPIO5 pins .........................................................................................1 mA Maximum output current sunk by GPIO0 pin ............................................................................................................4 mA Maximum output current sourced by GPIO0 pin .......................................................................................................4 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOL x IOL)
NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
(c) 2006 Microchip Technology Inc.
Advance Information
DS39776A-page 41
MRF24J40
TABLE 10-1: RECOMMENDED OPERATING CONDITIONS
Parameters Ambient Operating Temperature Supply Voltage for RF, Analog and Digital Circuits Supply Voltage for Digital I/O Input High Voltage (VIH) Input Low Voltage (VIL) Min -40 2.4 2.4 0.5 x VDD -0.3 Typ -- -- 3.3 -- -- Max +85 3.6 3.6 VDD + 0.3 0.2 x VDD Units C V V V V
TABLE 10-2:
CURRENT CONSUMPTION
Typical Values: TA = 25C, VDD = 3.3V Chip Mode Sleep TX RX Legend: TBD = To Be Determined At maximum output power Condition Min -- -- -- Typ 2 22 18 Max TBD TBD TBD Units A mA mA
TABLE 10-3:
RECEIVER AC CHARACTERISTICS
Typical Values: TA = 25C, VDD = 3.3V, LO Frequency = 2.445 GHz Parameters RF Input Frequency RF Sensitivity Maximum RF Input LO Leakage Input Return Loss Noise Figure (including matching) Adjacent Channel Rejection Alternate Channel Rejection RSSI Range RSSI Error @ +/- 5 MHz @ +/- 10 MHz At antenna input with O-QPSK signal and 3.5 dB front end loss is assumed LNA at high gain Measured at balun matching network input at frequency 2.405-2.48 GHz Externally matched to 50 source by a balun matching network Condition Min 2.4 -- +5 -- -12 -- 30 40 -- -5 Typ -- -91 -- -60 -20 8 -- -- 50 -- Max 2.483 -- -- -- -- -- -- -- -- 5 Units GHz dBm dBm dBm dB dB dB dB dB dB
DS39776A-page 42
Advance Information
(c) 2006 Microchip Technology Inc.
MRF24J40
TABLE 10-4: TRANSMITTER AC CHARACTERISTICS
Typical Values: TA = 25C, VDD = 3.3V, LO Frequency = 2.445 GHz Parameters RF Carrier Frequency Maximum RF Output Power RF Output Power Control Range TX Gain Control Resolution Carrier Suppression TX Spectrum Mask for O-QPSK Signal TX EVM TX Noise Floor Offset frequency > 3.5 MHz, at 0 dBm output power Programmed by register Condition Min 2.4 -- -- -- -- -33 -- -- Typ -- 0 38.75 1.25 -30 -- -- -- Max 2.483 -- -- -- -- -- 25 -126 Units GHz dBm dB dB dBc dBm % dBm/Hz
FIGURE 10-1:
82 CS
EXAMPLE SPI SLAVE MODE TIMING
70 SCK 71 72 80 83
SDO
MSb 75, 76
bit 6 - - - - - - 1
LSb 77
SDI
MSb In 74
bit 6 - - - - 1
LSb In
TABLE 10-5:
Param No. 70 71 72 74 75 76 78 80 82 83
EXAMPLE SPI SLAVE MODE REQUIREMENTS
Characteristic CS to SCK Input SCK Input High Time SCK Input Low Time SDO Data Output Rise Time SDO Data Output Fall Time SCK Output Rise Time (Master mode) Single Byte Single Byte Min 50 50 50 25 -- -- -- TBD TBD 50 Max Units Conditions -- -- -- -- 25 25 25 -- -- -- ns ns ns ns ns ns ns ns ns ns
Symbol TSSL2SCH TSCH TSCL TSCH2DIL TDOR TDOF TSCR
Hold Time of SDI Data Input to SCK Edge
TSCH2DOV, SDO Data Output Valid after SCK Edge TSCL2DOV TSSL2DOV TSCL2SSH SDO Data Output Valid after CS Edge CS after SCK Edge
Legend: TBD = To Be Determined
(c) 2006 Microchip Technology Inc.
Advance Information
DS39776A-page 43
MRF24J40
NOTES:
DS39776A-page 44
Advance Information
(c) 2006 Microchip Technology Inc.
MRF24J40
11.0
11.1
PACKAGING INFORMATION
Package Marking Information
40-Lead QFN
Example
XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN
MRF24J40 -I/MM e3 0610017
Legend: XX...X Y YY WW NNN
e3
*
Product-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
(c) 2006 Microchip Technology Inc.
Advance Information
DS39776A-page 45
MRF24J40
11.2 Package Details
The following sections give the technical details of the packages.
40-Lead Plastic Quad Flat, No Lead Package (MM) 6x6x0.9 mm Body [QFN] With 0.40 mm Contact Length
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D EXPOSED PAD
D2
e
E
E2 b
2 1 N NOTE 1
2 1 N L
K
TOP VIEW
BOTTOM VIEW
A
A3
A1
Units Dimension Limits Number of Pins N Pitch e Overall Height A Standoff A1 Contact Thickness A3 Overall Width E Exposed Pad Width E2 Overall Length D Exposed Pad Length D2 Contact Width b Contact Length L Contact-to-Exposed Pad K
MIN
0.80 0.00
4.00 4.00 0.18 0.30 0.20
MILLIMETERS NOM 40 0.50 BSC 0.90 0.02 0.20 REF 6.00 BSC 4.37 6.00 BSC 4.37 0.25 0.40 --
MAX
1.00 0.05
4.75 4.75 0.30 0.50 --
Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Significant Characteristic 3. Package is saw singulated 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing No. C04-118, 09/15/06
DS39776A-page 46
Advance Information
(c) 2006 Microchip Technology Inc.
MRF24J40
APPENDIX A:
A.1
LAYOUT AND PART SELECTION
Layout Considerations and RF Measurements
Below is an example of the circuit diagram of a balun. A balun is the impedance transformer from unbalanced input of the PCB antenna and the balanced input of the RF transceiver (pins RFP and RFN).
Figure A-2 shows the measured impedance of the balun where the center of the band is very close to 50. When using low tolerance components (i.e., 5%) along with an appropriate ground, the impedance will remain close to the 50 measurement. Figure A-3 shows the measured impedance of the PCB antenna using a logarithmic scale magnitude. Figure A-4 shows the same impedance using a Smith Chart diagram and Figure A-5 using a voltage standing wave ratio.
FIGURE A-1:
EXAMPLE CIRCUIT DIAGRAM
C40 100 nF
10 nH ANT
--GND
L5
L1 4.7 nH
C38 0.5 pF
RFP C43 0.5 pF L4 10 nH
0.3 pF C7
0.5 pF C23 L3 5.6 nH 0.5 pF C37
RFN
FIGURE A-2:
MEASURED IMPEDANCE
(c) 2006 Microchip Technology Inc.
Advance Information
DS39776A-page 47
MRF24J40
FIGURE A-3: IMPEDANCE OF THE PCB ANTENNA
FIGURE A-4:
IMPEDANCE OF THE PCB ANTENNA IN SMITH CHART
DS39776A-page 48
Advance Information
(c) 2006 Microchip Technology Inc.
MRF24J40
FIGURE A-5: IMPEDANCE OF THE PCB ANTENNA WITH VOLTAGE STANDING WAVE RATIO
The most critical part of maintaining proper impedance is adhering to the specified dimensions of the printed circuit board antenna (see Figure A-6). The antenna dimensions, if altered, will change the specified impedance. As an example, a 1 mm variance will shift the impedance by 5-10 MHz.
Note:
This part has been simulated using a HFSSTM simulator provided by Ansoft Corporation.
FIGURE A-6:
PRINTED CIRCUIT BOARD ANTENNA DIMENSIONS
22.0 1.3
1.0 6.0 8.6 3.8 5.3 0.85 3.37
2.0
4.2 3.82 4.3 1.54 0.5 1.2 0.5 1.0 1.0 1.0 1.0 6.6
1.2
0.72
(c) 2006 Microchip Technology Inc.
Advance Information
DS39776A-page 49
MRF24J40
Figure A-7 and Figure A-8 illustrate simulation results of this PCB antenna. Note the simulation results are very close to the measurements.
FIGURE A-7:
SIMULATED PCB ANTENNA IMPEDANCE, XY PLOT
DS39776A-page 50
Advance Information
(c) 2006 Microchip Technology Inc.
MRF24J40
FIGURE A-8: SIMULATED PCB ANTENNA IMPEDANCE, SMITH PLOT
(c) 2006 Microchip Technology Inc.
Advance Information
DS39776A-page 51
MRF24J40
A.2 PCB Layout Design
The following guidelines are intended to aid users who are not experienced in high-frequency PCB layout design. The printed circuit board is comprised of four basic FR4 layers: signal layout, RF ground, power line routing and ground (see Figure A-9). The guidelines will explain the requirements of these layers.
FIGURE A-9:
FOUR BASIC COPPER FR4 LAYERS
Signal Layout, Thickness = 1.8 mils Dielectric = 4.5, Thickness = 7 mils
RF Ground, Thickness = 1.2 mils
Dielectric = 4.5, Thickness = 19 mils
Power Line Routing, Thickness = 1.2 mils Dielectric = 4.5, Thickness = 7 mils Ground, Thickness = 1.8 mils Note: Care should be taken with all ground lines to prevent breakage.
* It is important to keep the original PCB thickness since any change will affect antenna performance (see total thickness of dielectric) or microstrip lines characteristic impedance. * The first layer width of a 50 characteristic impedance microstrip line is 12 mils. * Avoid having microstrip lines longer than 2.5 cm, since that line might get very close to a quarter wave length of the working frequency of the board which is 3.0 cm, and start behaving as an antenna. * Except for the antenna layout, avoid sharp corners since they can act as an antenna. Round corners will eliminate possible future EMI problems. * Digital lines by definition are prone to be very noisy when handling periodic waveforms and fast clock/switching rates. Avoid laying out a RF signal close to any digital lines.
* A via filled ground patch underneath the IC transceiver is mandatory. * A power supply must be distributed to each pin in a star topology and low-ESR capacitors must be placed at each pin for proper decoupling noise. * Decoupling each power pin is a tedious task, especially when the noise is affecting the performance of the transceiver in a specific bandwidth. Usually, low value caps (15-27 pF) combined with large value caps (100 nF) will cover a large spectrum of frequency. * Passive components (inductors) must be in the high-frequency category and the SRF (SelfResonant Frequency) should be at least two times higher than the operating frequency. Figure A-10 and Figure A-11 illustrate the ground and power plane for the RF board.
DS39776A-page 52
Advance Information
(c) 2006 Microchip Technology Inc.
MRF24J40
FIGURE A-10: GROUND PLANE FIGURE A-11: POWER GROUND PLANE
M
Antenna
Note:
See Figure A-6 for antenna dimensions
(c) 2006 Microchip Technology Inc.
Advance Information
DS39776A-page 53
MRF24J40
NOTES:
DS39776A-page 54
Advance Information
(c) 2006 Microchip Technology Inc.
APPENDIX B:
MRF24J40 SCHEMATIC AND BILL OF MATERIALS
B.1
Schematic
FIGURE B-1:
+3.3V C19 +3.3V C52 10 nF R20 +3.3V C53 20 pF +3.3V 2.2 F C40 47 pF L5 C48
40 35 34 31 VDD 39 NC 38
MRF24J40 SCHEMATIC
--GND
VDD
VDD 32
GND 36
LCAP
OSC1
C7
1 VDD_RF1_3V RFP RFN VDD VDD GND GPIO0 GPIO1 GPIO5 GPIO4 RXQP 30
C23 5.6 nH C37
3
L3 L4
2 RXIP 29 LPOSC1 28 LPOSC2 27 CLKOUT 26 GND 25 GND 24 NC 23 GND 22 VDD 21
0.3 pF 10 nH
4
0.5 pF
OSC2 33
0.5 pF
VDD 37
VDD
GPIO2
GPIO3
RESET
GND
WAKE
INT
SDO
SDI
SCK
11
12
13
14
15
16
17
18
19
20
CS
RB0/INT
(c) 2006 Microchip Technology Inc.
27 pF 0 C21 20 MHz Y3 20 pF C54 C39 100 nF 10 nH 0.5 pF 180 pF C58 27 pF +3.3V +3.3V C55 27 pF C38 C43 Y1 0.5 pF +3.3V C44
6 5
ANT
L1
4.7 nH
MRF24J40
C60 NL
NL 32.768 kHz
C64 NL
27 pF
7 8 9
Advance Information
+3.3V
10
Optional
C45 100 nF
+3.3V C63 R19 +3.3V 10K 10 nF
GPIO
SPI Module
GPIO OSC1
PIC(R) Microcontroller
MRF24J40
DS39776A-page 55
Note:
Center pad on QFN package must be grounded.
MRF24J40
B.2 Bill of Materials
MRF24J40 DAUGHTER CARD BILL OF MATERIALS
Reference Description C1 C23, C37, C38, C43 C21, C54 C19, C44, C55, C58 C40 C52, C63 Value Description Vendor Vendor # T491B225K025AT
TABLE B-1:
Quantity 1 4 2 4 1 2
Component Name CAP3528 CAP0402 CAP0402 CAP0402 CAP0402 CAP0402
2.2 F_Tant Capacitor TANT, Kemet 2.2 F, 25V, 10%, SMD 0.5 pF 20 pF 27 pF 47 pF 10 nF CAP, Ceramic, 0.5 pF, 50V, NP0, 0402 CAP, Ceramic, 20 pF, 50V, 5%, C0G, 0402 CAP, Ceramic, 27 pF, 50V, 0402, SMD CAP, Ceramic, 47 pF, 50V, C0G, 5%, 0402 CAP, Ceramic, 10000 pF, 16V, X7R, 0402 C0402C104K8PACTU CAP, Ceramic, 180 pF, 50V, C0G, 5%, 0402 CAP, Ceramic, 2.2 F, 10V, Y5V, 0603 Crystal, 20.000 MHz, 18 pF, FUND, SMD MRF24J40, Single Chip Transceiver 4.7 nH 5.6 nH 10 nH 0 10K Inductor Multilayer, 4.7 nH, 0402 Inductor Multilayer, 5.6 nH, 0402 Inductor Multilayer, 10 nH, 0402 RES, 0, 1/16W, 5%, 0402, SMD RES, 10 k, 1/16W, 5%, 0402, SMD .100" Socket/Terminal
Yageo America 0402CG508C9B200 Murata Electronics Panasonic ECG TDK Corporation Kemet GRM1555C1H200JZ01D ECJ-0EC1H270J C1005C0G1H470J C0402C103K4RACTU
2 1 1 1 1 1 1 2 2 1 1
CAP0402 CAP0402 CAP0603 CRYSTAL_ABM8 MRF24J40_QLP40 IND0402 IND0402 IND0402 RES0402 RES0402 HDR6X2
C39, C45 C48 C53 Y3 U1 L1 L3 L4, L5 R20, R22 R19 J2
100 nF 180 pF 2.2 F 20 MHz
Kemet TDK Corporation Taiyo Yuden Abracon Corporation Microchip TDK Corporation TDK Corporation TDK Corporation Panasonic ECG
C0402C104K8PACTU C1005C0G1H181J LMK107F225ZA-T ABM8-20.000MHZ-B2-T MRF24J40-I/ML MLK1005S4N7S MLK1005S5N6D MLK1005S10NJ ERJ-2GE0R00X
Yageo America RC0402JR-0710KL Samtec LST-106-07-F-D
DS39776A-page 56
Advance Information
(c) 2006 Microchip Technology Inc.
MRF24J40
B.3 REVISION HISTORY Revision A (December 2006)
Original data sheet for the MRF24J40 device.
(c) 2006 Microchip Technology Inc.
Advance Information
DS39776A-page 57
MRF24J40
NOTES:
DS39776A-page 58
Advance Information
(c) 2006 Microchip Technology Inc.
MRF24J40
INDEX
A
Absolute Maximum Ratings ................................................41 AC Characteristics Receiver .....................................................................42 Transmitter .................................................................43
G
General Purpose I/O .......................................................... 39 GPIO Registers TRISGPIO GPIO Pin Direction and SPI Mode Register ..................................... 40
I
IEEE 802.15.4 ...................................................................... 3 IEEE 802.15.4-2003 ........................................................... 19 Impedance Measured ................................................................... 47 PCB Antenna ............................................................. 48 PCB Antenna in Smith Chart ...................................... 48 PCB Antenna with Voltage Standing Wave Ratio ........................................................ 49 Simulated PCB Antenna, Smith Plot .......................... 51 Simulated PCB Antenna, XY Plot .............................. 50 Initialization ........................................................................ 21 Integrated Oscillator Drive .................................................... 3 Internet Address ................................................................. 61 Interrupts ............................................................................ 35 Structure ..................................................................... 35
B
Bill of Materials ...................................................................56 Block Diagrams Example Circuit ..........................................................47 Interrupt Logic .............................................................35 MRF24J40 Architecture ................................................4 Packet Format ............................................................19 Buffer Interface ...................................................................17
C
CCA Clear Channel Assessment ........................................30 Channel Selection ..............................................................24 Code Examples GPIO Read/Write ........................................................39 Initializing the MRF24J40 ...........................................28 Long Address Read ....................................................16 Long Address Write ....................................................17 Short Address Read ...................................................14 Short Address Write ...................................................15 Control Registers Long Address ...............................................................9 Mapping, Long Address ..............................................10 Mapping, Short Address .............................................10 Short Address ...............................................................9 COORD Bit .........................................................................24 CSMA-CA ...........................................................................29 Carrier Sense Multiple Access Collision Avoidance ............................................30 Current Consumption .....................................................3, 42 Customer Change Notification Service ...............................61 Customer Notification Service ............................................61 Customer Support ..............................................................61
L
Layout Considerations ....................................................... 47 Long Address Register Interface ........................................ 16 Reading ...................................................................... 16 Writing ........................................................................ 17 Long Address Summary ..................................................... 11 Long Addresses ................................................................. 26
M
MAC Initialization ............................................................... 24 Memory Organization ........................................................... 9 Microchip Internet Web Site ............................................... 61
P
Packages ............................................................................. 3 Packaging .......................................................................... 45 Details ........................................................................ 46 Marking ...................................................................... 45 Packet Format .................................................................... 19 Cyclic Redundancy Check (CRC) .............................. 19 Data Field ................................................................... 20 Data Payload .............................................................. 19 Destination Address ................................................... 19 Destination Address Fields ........................................ 20 FCS Field ................................................................... 20 Frame Control Field ................................................... 20 Frame Delimiter .......................................................... 20 Length Field ......................................................... 19, 20 Sequence Number Field ............................................ 20 Source Address .......................................................... 19 Source Address Fields ............................................... 20 PAN ID ............................................................................... 26 PANCOORD Bit ................................................................. 24 PCB Ground plane ............................................................. 53 Layout Design ............................................................ 52 Power Ground Plane .................................................. 53
D
Device Configuration ..........................................................24 Device Overview ...................................................................3 Features (40-Pin Devices) ............................................3 Differential RF Pin Negative RFN ......................................................................8 Positive RFP ......................................................................8
E
Electrical Characteristics ....................................................41 Errata ....................................................................................2 Example SPI Slave Mode Requirements ...........................43 Extended Organizationally Unique Identifier (EUI) .............20 External Connections ...........................................................7 CLKOUT Pin .................................................................7 Oscillator .......................................................................7 Start-up .................................................................7
(c) 2006 Microchip Technology Inc.
Advance Information
DS39776A-page 59
MRF24J40
PCB Antenna Dimensions ................................................................ 49 Simulation Results ..................................................... 50 PHY Initialization ................................................................ 22 Pin Descriptions ................................................................... 5 CLKOUT (Clock Output) .............................................. 5 CS (Serial Interface Enable) ........................................ 5 GND (Ground, Digital Circuit) ...................................... 5 GND (Ground, PLL) ..................................................... 5 GND (Guard Ring Ground) .......................................... 5 GPIO0 (External PA Enable) ....................................... 5 GPIO1 (External TX/RX Switch Control) ...................... 5 GPIO2 (External TX/RX Switch Control) ...................... 5 GPIO3 (General Purpose Digital I/O) ........................... 5 GPIO4 (General Purpose Digital I/O) ........................... 5 GPIO5 (General Purpose Digital I/O) ........................... 5 INT (Interrupt Pin) ........................................................ 5 LCAP (PLL Loop Filter External Capacitor) ................. 5 LPOSC1 (32 kHz Crystal Input) ................................... 5 LPOSC2 (32 kHz Crystal Input) ................................... 5 NC (No Connection) ..................................................... 5 OSC1 (20 MHz Crystal Input) ...................................... 5 OSC2 (20 MHz Crystal Input) ...................................... 5 RESET (Global Hardware Reset Active-Low) .............. 5 RFN (Differential RF Pin, Negative) ............................. 5 RFP (Differential RF Pin, Positive) ............................... 5 RXIP (Analog RX I Channel Output) ............................ 5 RXQP (Analog RX Q Channel Output) ........................ 5 SCK (Serial Interface Clock) ........................................ 5 SDI (Serial Interface Data Input) .................................. 5 SDO (Serial Interface Data Output) ............................. 5 VDD (Charge Pump Power Supply) .............................. 5 VDD (Digital Circuit Power Supply) ............................... 5 VDD (Guard Ring Power Supply) .................................. 5 VDD (PLL Power Supply) .............................................. 5 VDD (Power Supply, Analog Circuit) ............................. 5 VDD (Power Supply, Band Gap Reference Circuit) ................................................ 5 VDD (RF Power Supply) ............................................... 5 VDD (VCO Supply) ....................................................... 5 WAKE (External Wake-up Trigger) .............................. 5 Power-Saving Mode ............................................................. 3 Proprietary Protocols ............................................................ 1 MiWi ............................................................................. 1 ZigBee ...................................................................... 1, 9 ISRSTS (Interrupt Status) .......................................... 36 PANIDH (MAC PAN High Byte) ................................. 26 PANIDL (MAC PAN Low Byte) .................................. 26 RFCTL (RF Mode Control) ........................................ 24 RFCTRL0 (RF Control 0) ........................................... 24 RFCTRL2 (RF Control 2) ........................................... 22 RFCTRL3 (RF Control 3) ........................................... 22 RFCTRL6 (RF Control 6) ........................................... 23 RFCTRL7 (RF Control 7) ............................................. 8 RFCTRL8 (RF Control 8) ........................................... 23 RSSITHCCA (RSSI Threshold for CCA) ................... 23 RXFLUSH (Receive FIFO Flush) ............................... 34 RXMCR (Receive Filter Control) ................................ 21 SADRH (MAC Short Address High Byte) .................. 27 SADRL (MAC Short Address Low Byte) .................... 27 TRISGPIO (GPIO Pin Direction and SPI Mode) ................................................... 40 TXNMTRIG (Trigger and Setting for Normal Frame, CAP) .................................... 30 TXSR (TX MAC Status) ............................................. 31 RF Measurements ............................................................. 47 RF Output ............................................................................ 8 RF Transceiver .................................................................. 47 RSSI Default Threshold ..................................................... 22 RX FIFO ............................................................................. 31 RX MAC ............................................................................. 31
S
Schematic .......................................................................... 55 Security Buffer ..................................................................... 9 Serial Communications ........................................................ 3 Serial Peripheral Interface (SPI) ........................................ 13 Short Address Register Interface ....................................... 14 Reading ..................................................................... 14 Writing ....................................................................... 15 Short Address Summary .................................................... 11 Short Addresses ................................................................ 26 Sleep Mode .......................................................................... 3
T
Timing Diagrams Example SPI Slave Mode .......................................... 43 Long Address Read ................................................... 16 Long Address Write ................................................... 17 Short Address Read .................................................. 14 Short Address Write ................................................... 15 SPI Input .................................................................... 13 SPI Output ................................................................. 13 Transmit Buffers .................................................................. 9 Transmit Packets ............................................................... 21 Transmitting Packets ......................................................... 29 Status ........................................................................ 31 Trigger Packet ........................................................... 30 TX FIFO ............................................................................. 30 TX FIFO Format ................................................................. 29 TX MAC ............................................................................. 29
R
Reader Response .............................................................. 62 Receive Buffers .................................................................... 9 Receive Filters ................................................................... 21 Receive Packets ................................................................ 21 Receive Process Flowchart ................................................ 32 Receiving Packets .............................................................. 31 Freeing Buffer Space ................................................. 34 Layout ........................................................................ 33 Recommended Operating Conditions ................................ 42 Reference Clock Output ....................................................... 3 Register File Summary ....................................................... 11 Registers BBREG2 (Baseband CCA/RSSI Mode 2) .................. 25 BBREG6 (Baseband RSSI Mode 6) .......................... 25 CLKCTRL (Divided Sleep Clock Selection) ................. 7 CLKINTCR (SLPCLK On/Off and Interrupt Polarity) ............................................... 38 GPIO (GPIO Port) ...................................................... 39 INTMSK (Interrupt Mask) ........................................... 37
W
WWW Address .................................................................. 61 WWW, On-Line Support ...................................................... 2
Z
Zigbee V1.0 Specification .................................................... 9
DS39776A-page 60
Advance Information
(c) 2006 Microchip Technology Inc.
MRF24J40
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels: * * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions.
(c) 2006 Microchip Technology Inc.
Advance Information
DS39776A-page 61
MRF24J40
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: MRF24J40 Questions: 1. What are the best features of this document? Y N Literature Number: DS39776A FAX: (______) _________ - _________
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS39776A-page 62
Advance Information
(c) 2006 Microchip Technology Inc.
MRF24J40
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package XXX Pattern
Example: a) MRF24J40-I/MM: Industrial temperature, QFN package.
Device
MRF24J40: IEEE 802.15.4TM 2.4 GHz RF Transceiver
Temperature Range
I
= -40C to +85C (Industrial)
Package
MM = QFN (Plastic Quad Flat, No Lead)
(c) 2006 Microchip Technology Inc.
Advance Information
DS39776A-page 63
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Alpharetta, GA Tel: 770-640-0034 Fax: 770-640-0307 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Habour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Fuzhou Tel: 86-591-8750-3506 Fax: 86-591-8750-3521 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Shunde Tel: 86-757-2839-5507 Fax: 86-757-2839-5571 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7250 Fax: 86-29-8833-7256
ASIA/PACIFIC
India - Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Gumi Tel: 82-54-473-4301 Fax: 82-54-473-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Penang Tel: 60-4-646-8870 Fax: 60-4-646-5086 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350
EUROPE
Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820
10/19/06
DS39776A-page 64
Advance Information
(c) 2006 Microchip Technology Inc.

▲Up To Search▲

Price & Availability of MRF24J40-I

	To Download MRF24J40-I Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .